Clock Hold warning

Maybe this can help you:

http://quartushelp.altera.com/current/mergedprojects/analyze/tan/tan_gid_hold_violate.htm

There's also a bunch of threads regarding hold violations arround here.

--- Quote Start ---

Hello friends,

I have complete and simulate some design for MAX3000A.

I have one warning I cannot avoid

Warning: Can't achieve minimum setup and hold requirement clock_in along 8 path(s). See Report window for details.

I need max. 1MHz clock. I defined 1MHz as default Fmax and also I defined individual clock 1MHz my net with external clock(is this right?)

Timing Analyzer says at Clock Hold report:

Required shortest P2P 2.9nS and Actual P2P 2.6nS.... for 8 paths (it's from one verilog module to another).

Now how can I deal with it?

Thanks very much for further advices,

--- Quote End ---

Hi,

can you explain more detailed how your design lookslike ? How is the clock generated and distributed ?

Kind regards

GPK

Hello again,

I solved somehow, thanks link above :)

Since I had negative skew, I had to insert eight LCELLs on that bus path.

Now I've done from schematic and worked very well, but have no idea how to solve from verilog.

So I need some LCELL equivalent logic in verilog.

--- Quote Start ---

Hello again,

I solved somehow, thanks link above :)

Since I had negative skew, I had to insert eight LCELLs on that bus path.

Now I've done from schematic and worked very well, but have no idea how to solve from verilog.

So I need some LCELL equivalent logic in verilog.

--- Quote End ---

Hi,

For Verilog you can use:

LCELL <instance_name> (.in(<input_wire>), .out(<output_wire>));

BTW: Did you run a fast timing analysis also ? The delay caused by the LCELL depends on the power supply, temperature and device speed. Maybe your eight LCELL are not sufficient in case of fast timing conditions.

Kind regards

GPK

Thank you pletz, I'll modify soon...

But back to trouble :rolleyes:... once I assigned pins to my PLD and prepare to program'it... the timing problems went back again.

Now I had -7.400nS min. slack for that 8 bus lines without LCELLs and -0.7nS with LCELLs. I need few delays more and I really don't know from where to get. Required shortest P2P 13.1nS and I have 5.7nS.

I inserted a 74244 buffer but for nothing... seems compiler is so smart to ignore it. What should I do?

Thanks in advance,

--- Quote Start ---

Thank you pletz, I'll modify soon...

But back to trouble :rolleyes:... once I assigned pins to my PLD and prepare to program'it... the timing problems went back again.

Now I had -7.400nS min. slack for that 8 bus lines without LCELLs and -0.7nS with LCELLs. I need few delays more and I really don't know from where to get. Required shortest P2P 13.1nS and I have 5.7nS.

I inserted a 74244 buffer but for nothing... seems compiler is so smart to ignore it. What should I do?

Thanks in advance,

--- Quote End ---

Hi,

we have to find out where the skew comes from ! Is it possible for you to post your design or parts of it in the forum, so that I can have a brief look to it ?

Kind regards

GPK

Thanks pletz (and all), finally solved.

It was my faulty design (mixed schematic and verilog). Basically I was trying to do several consecutive operations on the same posedge. I create a tmp reg variable and then use it to copy desired data @ unused negedge of master clock. Now everything is in verilog.

I guess LCELL delay was anyhow a compromise sollution that should be avoided.

I'm not clear with fast timing analysis you said. I have run Classic Timing Analysis and everything is ok from 1KHz to 10MHz. Actually it reports somewhere around 29MHz limit on my design (portions) which is anyhow far enough for me. This is a transcoder from serial stream (synchron) to parallel bus and vicecersa (bidir) up to 153Kbps.

--- Quote Start ---

Thanks pletz (and all), finally solved.

It was my faulty design (mixed schematic and verilog). Basically I was trying to do several consecutive operations on the same posedge. I create a tmp reg variable and then use it to copy desired data @ unused negedge of master clock. Now everything is in verilog.

I guess LCELL delay was anyhow a compromise sollution that should be avoided.

I'm not clear with fast timing analysis you said. I have run Classic Timing Analysis and everything is ok from 1KHz to 10MHz. Actually it reports somewhere around 29MHz limit on my design (portions) which is anyhow far enough for me. This is a transcoder from serial stream (synchron) to parallel bus and vicecersa (bidir) up to 153Kbps.

--- Quote End ---

Hi,

did you solve your hold time problems ?

As default the classic timing analyzer uses the worst-case parameter, means slowest process, low power supply and high temperature. You have to check the hold time also

with the fast parameter to be sure that it works also.

You can run a fast timing analysis :

Processing -> Start -> Start Classic Timing Analyzer (Fast Timing Model)

Kind regards

GPK

Yes, all clock hold timing problems are resolved now. In fact, from 1KHz (and lower) up to 29MHz there are no more violations reported by Classic Timing Analyzer, so I supposed everything is ok now.

I cannot run

Processing -> Start -> Start Classic Timing Analyzer (Fast Timing Model)

(thanks for tip) because it reports this is not supported by my MAX3000 family. However, Constraint check -> success

Tnx again,