Clock Hold warning

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Hello friends,

I have complete and simulate some design for MAX3000A.

I have one warning I cannot avoid

Warning: Can't achieve minimum setup and hold requirement clock_in along 8 path(s). See Report window for details.

I need max. 1MHz clock. I defined 1MHz as default Fmax and also I defined individual clock 1MHz my net with external clock(is this right?)

Timing Analyzer says at Clock Hold report:

Required shortest P2P 2.9nS and Actual P2P 2.6nS.... for 8 paths (it's from one verilog module to another).

Now how can I deal with it?

Thanks very much for further advices,

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Hi,

can you explain more detailed how your design lookslike ? How is the clock generated and distributed ?

Kind regards

GPK