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Altera_Forum's avatar
Altera_Forum
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16 years ago

Clock Hold warning

Hello friends, I have complete and simulate some design for MAX3000A. I have one warning I cannot avoid Warning: Can't achieve minimum setup and hold requirement clock_in along 8 path(s)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Yes, all clock hold timing problems are resolved now. In fact, from 1KHz (and lower) up to 29MHz there are no more violations reported by Classic Timing Analyzer, so I supposed everything is ok now.

I cannot run

Processing -> Start -> Start Classic Timing Analyzer (Fast Timing Model)

(thanks for tip) because it reports this is not supported by my MAX3000 family. However, Constraint check -> success

Tnx again,