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Altera_Forum's avatar
Altera_Forum
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16 years ago

Clock Hold warning

Hello friends, I have complete and simulate some design for MAX3000A. I have one warning I cannot avoid Warning: Can't achieve minimum setup and hold requirement clock_in along 8 path(s)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Thank you pletz, I'll modify soon...

But back to trouble :rolleyes:... once I assigned pins to my PLD and prepare to program'it... the timing problems went back again.

Now I had -7.400nS min. slack for that 8 bus lines without LCELLs and -0.7nS with LCELLs. I need few delays more and I really don't know from where to get. Required shortest P2P 13.1nS and I have 5.7nS.

I inserted a 74244 buffer but for nothing... seems compiler is so smart to ignore it. What should I do?

Thanks in advance,

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Hi,

we have to find out where the skew comes from ! Is it possible for you to post your design or parts of it in the forum, so that I can have a brief look to it ?

Kind regards

GPK