Clock Hold warning

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Hello again,

I solved somehow, thanks link above :)

Since I had negative skew, I had to insert eight LCELLs on that bus path.

Now I've done from schematic and worked very well, but have no idea how to solve from verilog.

So I need some LCELL equivalent logic in verilog.

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Hi,

For Verilog you can use:

LCELL <instance_name> (.in(<input_wire>), .out(<output_wire>));

BTW: Did you run a fast timing analysis also ? The delay caused by the LCELL depends on the power supply, temperature and device speed. Maybe your eight LCELL are not sufficient in case of fast timing conditions.

Kind regards

GPK