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Altera_Forum's avatar
Altera_Forum
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16 years ago

Clock Hold warning

Hello friends, I have complete and simulate some design for MAX3000A. I have one warning I cannot avoid Warning: Can't achieve minimum setup and hold requirement clock_in along 8 path(s)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello again,

I solved somehow, thanks link above :)

Since I had negative skew, I had to insert eight LCELLs on that bus path.

Now I've done from schematic and worked very well, but have no idea how to solve from verilog.

So I need some LCELL equivalent logic in verilog.