Clock Hold warning

Thanks pletz (and all), finally solved.

It was my faulty design (mixed schematic and verilog). Basically I was trying to do several consecutive operations on the same posedge. I create a tmp reg variable and then use it to copy desired data @ unused negedge of master clock. Now everything is in verilog.

I guess LCELL delay was anyhow a compromise sollution that should be avoided.

I'm not clear with fast timing analysis you said. I have run Classic Timing Analysis and everything is ok from 1KHz to 10MHz. Actually it reports somewhere around 29MHz limit on my design (portions) which is anyhow far enough for me. This is a transcoder from serial stream (synchron) to parallel bus and vicecersa (bidir) up to 153Kbps.