Altera_Forum
Honored Contributor
Honored ContributorCIC Megacore
hi
i am tring to use the cic megacore from altera. but the core is just not running. i have made the following interface to it from my vhdl module:
component CIC port( clk : IN STD_LOGIC; clken : IN STD_LOGIC; reset_n : IN STD_LOGIC; in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); in_valid : IN STD_LOGIC; out_ready : IN STD_LOGIC; in_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0); out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); in_ready : OUT STD_LOGIC; out_valid : OUT STD_LOGIC; out_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) ); end component; ---------------------------------------------------------------- ---------------------Read CIC---------------------------------- ---------------------------------------------------------------- process (nreset,clk) begin if nreset ='1' then out_ready<='0'; cic_out<="0000000000000000"; clken<='0'; elsif RISING_EDGE(clk) and out_valid ='1' then clken<='0'; cic_out<=out_data; out_ready<='1'; read_out_error<=out_error; else out_ready<='0'; out_ready<=out_ready; end if; end process; ---------------------------------------------------------------- ---------------------Write CIC---------------------------------- ---------------------------------------------------------------- process (nreset,clk) begin if nreset ='1' then in_valid<='0'; in_error<="00"; elsif RISING_EDGE(clk) and in_ready ='1' then in_valid<='1'; tempMIC8bit<="00001111";--MIC8bit; in_error<="00"; else in_valid<='0'; in_valid<=in_valid; end if; --in_valid<=in_valid; end process; U2:CIC PORT map (clk,clken,nreset,tempMIC8bit,in_valid,out_ready,in_error,out_data,in_ready,out_valid,out_error); the only thing thats working is "in_ready" that goes high when i hit the reset btn :(
why is it not working? do i have to include som ekstra files? quartus has already included alot of cic files for the component.
i am using the guide from altera:
http://www.altera.com/literature/ug/ug_cic.pdf
br
benjamin
