hi i am tring to use the cic megacore from altera. but the core is just not running. i have made the following interface to it from my vhdl module: component CIC port( clk : IN STD_LOGIC; clken : IN STD_LOGIC; reset_n : IN STD_LOGIC; in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); in_valid : IN STD_LOGIC; out_ready : IN STD_LOGIC; in_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0); out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); in_ready : OUT STD_LOGIC; out_valid : OUT STD_LOGIC; out_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) ); end component; ---------------------------------------------------------------- ---------------------Read CIC---------------------------------- ---------------------------------------------------------------- process (nreset,clk) begin if nreset ='1' then out_ready<='0'; cic_out<="0000000000000000"; clken<='0'; elsif RISING_EDGE(clk) and out_valid ='1' then clken<='0'; cic_out<=out_data; out_ready<='1'; read_out_error<=out_error; else out_ready<='0'; out_ready<=out_ready; end if; end process; ---------------------------------------------------------------- ---------------------Write CIC---------------------------------- ---------------------------------------------------------------- process (nreset,clk) begin if nreset ='1' then in_valid<='0'; in_error<="00"; elsif RISING_EDGE(clk) and in_ready ='1' then in_valid<='1'; tempMIC8bit<="00001111";--MIC8bit; in_error<="00"; else in_valid<='0'; in_valid<=in_valid; end if; --in_valid<=in_valid; end process; U2:CIC PORT map (clk,clken,nreset,tempMIC8bit,in_valid,out_ready,in_error,out_data,in_ready,out_valid,out_error); the only thing thats working is "in_ready" that goes high when i hit the reset btn :( why is it not working? do i have to include som ekstra files? quartus has already included alot of cic files for the component. i am using the guide from altera: http://www.altera.com/literature/ug/ug_cic.pdf br benjamin

Hi, just one point about nReset. I assume it is negative logic i.e. when '0' it resets, when '1' it is released. kaz

Yes, it is inverted. Don´t know how to invert the value on the btn on the board.

But your two processes are using nReset as positive logic. This will clash with the CIC module edit: also notice that statements like: in_valid<='0'; in_valid<=in_valid; is not quite meaningful as last statement overwrites and is final at compile time kaz

Hi When I run my code nreset = 0, when I push the reset button on the board nreset = 1. It is inverted. Is CIC IP using a reset =1 to run?

It is standard naming convention that reset_n is active negative i.e. CIC is under reset when reset_n = '0' CIC is released for work when reset_n = '1' You may just invert your nreset then connect it to CIC(better change the name of nreset to reset) kaz

Forum Discussion

Altera_Forum

Honored Contributor

17 years ago

CIC Megacore

i am tring to use the cic megacore from altera. but the core is just not running. i have made the following interface to it from my vhdl module:

component CIC

port( clk : IN STD_LOGIC;

clken : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

in_valid : IN STD_LOGIC;

out_ready : IN STD_LOGIC;

in_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

in_ready : OUT STD_LOGIC;

out_valid : OUT STD_LOGIC;

out_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)

);

end component;

----------------------------------------------------------------

---------------------Read CIC----------------------------------

----------------------------------------------------------------

process (nreset,clk)

begin

if nreset ='1' then

out_ready<='0';

cic_out<="0000000000000000";

clken<='0';

elsif RISING_EDGE(clk) and out_valid ='1' then

clken<='0';

cic_out<=out_data;

out_ready<='1';

read_out_error<=out_error;

else

out_ready<='0';

out_ready<=out_ready;

end if;

end process;

----------------------------------------------------------------

---------------------Write CIC----------------------------------

----------------------------------------------------------------

process (nreset,clk)

begin

if nreset ='1' then

in_valid<='0';

in_error<="00";

elsif RISING_EDGE(clk) and in_ready ='1' then

in_valid<='1';

tempMIC8bit<="00001111";--MIC8bit;

in_error<="00";

else

in_valid<='0';

in_valid<=in_valid;

end if;

--in_valid<=in_valid;

end process;

U2:CIC PORT map (clk,clken,nreset,tempMIC8bit,in_valid,out_ready,in_error,out_data,in_ready,out_valid,out_error);

the only thing thats working is "in_ready" that goes high when i hit the reset btn :(

why is it not working? do i have to include som ekstra files? quartus has already included alot of cic files for the component.

i am using the guide from altera:

http://www.altera.com/literature/ug/ug_cic.pdf

benjamin

11 Replies

Altera_Forum
Honored Contributor
17 years ago
Hi,

just one point about nReset. I assume it is negative logic i.e. when '0' it resets, when '1' it is released.

kaz
Altera_Forum
Honored Contributor
17 years ago
Yes, it is inverted. Don´t know how to invert the value on the btn on the board.
Altera_Forum
Honored Contributor
17 years ago
But your two processes are using nReset as positive logic. This will clash with the CIC module

edit: also notice that statements like:

in_valid<='0';
in_valid<=in_valid;

is not quite meaningful as last statement overwrites and is final at compile
time

kaz
Altera_Forum
Honored Contributor
17 years ago
Hi

When I run my code nreset = 0, when I push the reset button on the board nreset = 1. It is inverted.

Is CIC IP using a reset =1 to run?
Altera_Forum
Honored Contributor
17 years ago
It is standard naming convention that reset_n is active negative i.e.
CIC is under reset when reset_n = '0'
CIC is released for work when reset_n = '1'

You may just invert your nreset then connect it to CIC(better change the name of nreset to reset)

kaz
Altera_Forum
Honored Contributor
17 years ago
hi

i have now changed my code to this:

----------------------------------------------------------------
---------------------Read CIC----------------------------------
----------------------------------------------------------------
process (reset_n,clk)
begin
if reset_n ='1' then
out_ready<='0';
cic_out<="0000000000000000";
clken<='0';
elsif RISING_EDGE(clk) and out_valid ='1' then
clken<='0';
cic_out<=out_data;
out_ready<='1';
read_out_error<=out_error;
else
out_ready<='0';
out_ready<=out_ready;
end if;
end process;
----------------------------------------------------------------
---------------------Write CIC----------------------------------
----------------------------------------------------------------
process (reset_n,clk)
begin
if reset_n ='1' then
in_valid<='0';
in_error<="00";
elsif RISING_EDGE(clk) and in_ready ='1' then
in_valid<='1';
tempMIC8bit<="00001111";--MIC8bit;
in_error<="00";
else
in_valid<='0';
in_valid<=in_valid;
end if;
--in_valid<=in_valid;
end process;

U2:CIC PORT map (clk,clken,reset_n,tempMIC8bit,in_valid,out_ready,in_error,out_data,in_ready,out_valid,out_error);

sorry had it wrong, but i have just made the change a little time ago in desperate hunt for the solution to this problem. this should be better. but the cic ip is still not running.

here is a picture of the signaltab:
http://nygaard1899.dk/signaltap.bmp

there is just not happening anything :(

br
benjamin
Altera_Forum
Honored Contributor
17 years ago
Hi,

You need some more work on your code.

-you are driving clken low always.
-reset is still not released
- statements like
in_valid<='0';
in_valid<=in_valid;
doesn't look right to me as the signal is updated in the sequential process at compile time.

I haven't use CIC core itself but many other cores and so can only help in general coding sense. Generally, with cores all you have to do is supply the right inputs to the core and connect the outputs.

kaz
Altera_Forum
Honored Contributor
17 years ago
Hi,

why not just remove the processes and do this:

U1:CIC
port map(
clk => clk,
clken => '1',
reset_n => reset_n,
in_data => x"0F0F0F0F",
in_valid => '1',

...etc.

kaz
Altera_Forum
Honored Contributor
17 years ago
Hi

I have changed the port mapping:

U2:CIC PORT map (clk=>clk,
clken=>'1',
reset_n=>reset_n,
in_data=>x"0F",
in_valid=>in_valid,
out_ready=>out_ready,
in_error=>in_error,
out_data=>out_data,
in_ready=>in_ready,
out_valid=>out_valid,
out_error=>out_error);

But there is still not happening anything
Altera_Forum
Honored Contributor
17 years ago
Hi,

All inputs should be connected and their logic identified. If it still doesn't work then you ned to check your core itself.

clk=>clk, --ok
clken=>'1', --ok
reset_n=>reset_n, -- make sure this signal goes high for operation
in_data=>x"0F", -- how is this accepted by compiler?? 8 to 32 bits
in_valid=>in_valid, -- may be this => '1' will do for now
out_ready=>out_ready, -- define this logic e.g. =>'1'
in_error=>in_error, -- define this logic
out_data=>out_data,
in_ready=>in_ready,
out_valid=>out_valid,
out_error=>out_error

kaz

Forum Discussion

CIC Megacore

11 Replies

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