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Altera_Forum's avatar
Altera_Forum
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17 years ago

CIC Megacore

hi i am tring to use the cic megacore from altera. but the core is just not running. i have made the following interface to it from my vhdl module: component CIC port( clk : IN ST...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi

I have changed the port mapping:

U2:CIC PORT map (clk=>clk,

clken=>'1',

reset_n=>reset_n,

in_data=>x"0F",

in_valid=>in_valid,

out_ready=>out_ready,

in_error=>in_error,

out_data=>out_data,

in_ready=>in_ready,

out_valid=>out_valid,

out_error=>out_error);

But there is still not happening anything