CIC Megacore

hi

i have now changed my code to this:

----------------------------------------------------------------

---------------------Read CIC----------------------------------

----------------------------------------------------------------

process (reset_n,clk)

begin

if reset_n ='1' then

out_ready<='0';

cic_out<="0000000000000000";

clken<='0';

elsif RISING_EDGE(clk) and out_valid ='1' then

clken<='0';

cic_out<=out_data;

out_ready<='1';

read_out_error<=out_error;

else

out_ready<='0';

out_ready<=out_ready;

end if;

end process;

----------------------------------------------------------------

---------------------Write CIC----------------------------------

----------------------------------------------------------------

process (reset_n,clk)

begin

if reset_n ='1' then

in_valid<='0';

in_error<="00";

elsif RISING_EDGE(clk) and in_ready ='1' then

in_valid<='1';

tempMIC8bit<="00001111";--MIC8bit;

in_error<="00";

else

in_valid<='0';

in_valid<=in_valid;

end if;

--in_valid<=in_valid;

end process;

U2:CIC PORT map (clk,clken,reset_n,tempMIC8bit,in_valid,out_ready,in_error,out_data,in_ready,out_valid,out_error);

sorry had it wrong, but i have just made the change a little time ago in desperate hunt for the solution to this problem. this should be better. but the cic ip is still not running.

here is a picture of the signaltab:

http://nygaard1899.dk/signaltap.bmp

there is just not happening anything :(

br

benjamin