Can not implement the requested PLL: VCO or PFD frequency range exceeded

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Hello, I need to scale 3.58 MHz 16 times up, to 57.28 MHz.

EP3C5 device. Minimum frequency I put to clear the error is 5 MHz.

I created project from the scratch, does it need some default setting to be changed? And is it possible to scale low frequencies up?

(I did not find answers in datasheet).

Thank you.

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One way to do this is to go through a digital 2x multiplication on the clock then feed the resulting signal out and back into a clock input for the PLL. Then do a 8x multiplication in the PLL.

Pete

Thank you both. Seems great in theory, but what is about implementation of it?

ATPLL does not digest 3.58. It handles frequency starting 5 MHz. Thus I do not see the way how to "create a altpll then set the multiplication to 2".

Hi Eugeny:

Basically the way we did it, was we had two clocks in the system. One fast clock that was already OK for a pll, and one slow clock that was not within spec for the input of a PLL.

We used the fastest clock in the system, and sampled the slow clock through multiple registers stages (You need 2 or greater to avoid metastability)

Then we xor'ed the original slow clock with the delayed sampled version. and drove this to an output pin of the FPGA, and back into a clock input for the PLL we needed to get our final multiplication factor.

The clock generated this way is not 50/50 duty cycle, but as long as your are close enough for the PLL input, you are good. You can change the number of delay stages to get as close as possible.

IE if you have a 100 MHz clock, you can sample and delay the 3.58 MHz by 7 10 ns periods, then XOR the original clock input with the 70 ns delayed version to generate a 7.16 MHz clock output that you then feed back into a PLL input.

Pete

Pete, thank you very much. You explanation is clear.

My design has only one, slow clock, which I wanted to scale up.

The intention of my question was to know if it is ever possible to feed PLL with such slow clock (e.g. changing some PLL or chip-level settings) properly.

If you confirm it is not possible in any circumstances, then I will just add the clock generator to the board - I still have this option because board is not yet finalized.

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Pete, thank you very much. You explanation is clear.

My design has only one, slow clock, which I wanted to scale up.

The intention of my question was to know if it is ever possible to feed PLL with such slow clock (e.g. changing some PLL or chip-level settings) properly.

If you confirm it is not possible in any circumstances, then I will just add the clock generator to the board - I still have this option because board is not yet finalized.

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With the cyclone III family (and IV, V and Max 10 families for that matter) the PLL datasheet fin minimum is stated at 5 MHz.

Is it possible to make PLL's that lock to frequencies < 5 MHz, yes, But the PLL's in the Cyclone fabric were designed with a 5 MHz minimum frequency target.

Will it work at 3.58 MHz input? Possible, but it won't be guaranteed, and a lock output may not be stable.

To try it you would have to setup your 16x multiplication as if you input clock was 5 MHz, and just run it with a 3.58 MHz source and run it and see. But even if it works at room temperature, it may not work at the hot/cold corners.

Pete

I think you will need the clock generator. It is a simple solution to your problem and a peace of mind.

You will need to meet the min 5Mhz spec.