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Altera_Forum
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10 years ago

Can not implement the requested PLL: VCO or PFD frequency range exceeded

Hello, I need to scale 3.58 MHz 16 times up, to 57.28 MHz. EP3C5 device. Minimum frequency I put to clear the error is 5 MHz. I created project from the scratch, does it need some default settin...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Hi Eugeny:

Basically the way we did it, was we had two clocks in the system. One fast clock that was already OK for a pll, and one slow clock that was not within spec for the input of a PLL.

We used the fastest clock in the system, and sampled the slow clock through multiple registers stages (You need 2 or greater to avoid metastability)

Then we xor'ed the original slow clock with the delayed sampled version. and drove this to an output pin of the FPGA, and back into a clock input for the PLL we needed to get our final multiplication factor.

The clock generated this way is not 50/50 duty cycle, but as long as your are close enough for the PLL input, you are good. You can change the number of delay stages to get as close as possible.

IE if you have a 100 MHz clock, you can sample and delay the 3.58 MHz by 7 10 ns periods, then XOR the original clock input with the 70 ns delayed version to generate a 7.16 MHz clock output that you then feed back into a PLL input.

Pete