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Altera_Forum
Honored Contributor
Honored ContributorCan not implement the requested PLL: VCO or PFD frequency range exceeded
Hello, I need to scale 3.58 MHz 16 times up, to 57.28 MHz. EP3C5 device. Minimum frequency I put to clear the error is 5 MHz. I created project from the scratch, does it need some default settin...
Altera_ForumHonored Contributor
Honored ContributorPete, as I understand you propose to use another two FPGA pins and some external "digital 2x multiplier". Is there a way doing the task internally to the FPGA? Why its PLL can not handle slow input clock?
