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Pete, thank you very much. You explanation is clear.
My design has only one, slow clock, which I wanted to scale up.
The intention of my question was to know if it is ever possible to feed PLL with such slow clock (e.g. changing some PLL or chip-level settings) properly.
If you confirm it is not possible in any circumstances, then I will just add the clock generator to the board - I still have this option because board is not yet finalized.
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With the cyclone III family (and IV, V and Max 10 families for that matter) the PLL datasheet fin minimum is stated at 5 MHz.
Is it possible to make PLL's that lock to frequencies < 5 MHz, yes, But the PLL's in the Cyclone fabric were designed with a 5 MHz minimum frequency target.
Will it work at 3.58 MHz input? Possible, but it won't be guaranteed, and a lock output may not be stable.
To try it you would have to setup your 16x multiplication as if you input clock was 5 MHz, and just run it with a 3.58 MHz source and run it and see. But even if it works at room temperature, it may not work at the hot/cold corners.
Pete
Honored Contributor
