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Altera_Forum
Honored Contributor
Honored ContributorCan not implement the requested PLL: VCO or PFD frequency range exceeded
Hello, I need to scale 3.58 MHz 16 times up, to 57.28 MHz. EP3C5 device. Minimum frequency I put to clear the error is 5 MHz. I created project from the scratch, does it need some default settin...
Altera_ForumHonored Contributor
Honored ContributorPete, thank you very much. You explanation is clear.
My design has only one, slow clock, which I wanted to scale up. The intention of my question was to know if it is ever possible to feed PLL with such slow clock (e.g. changing some PLL or chip-level settings) properly. If you confirm it is not possible in any circumstances, then I will just add the clock generator to the board - I still have this option because board is not yet finalized.
