Can not implement the requested PLL: VCO or PFD frequency range exceeded

Pete, thank you very much. You explanation is clear.

My design has only one, slow clock, which I wanted to scale up.

The intention of my question was to know if it is ever possible to feed PLL with such slow clock (e.g. changing some PLL or chip-level settings) properly.

If you confirm it is not possible in any circumstances, then I will just add the clock generator to the board - I still have this option because board is not yet finalized.