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Altera_Forum's avatar
Altera_Forum
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11 years ago

Can not implement the requested PLL: VCO or PFD frequency range exceeded

Hello, I need to scale 3.58 MHz 16 times up, to 57.28 MHz. EP3C5 device. Minimum frequency I put to clear the error is 5 MHz. I created project from the scratch, does it need some default settin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I think you will need the clock generator. It is a simple solution to your problem and a peace of mind.

You will need to meet the min 5Mhz spec.