Board recommendation for MLBS until 60MHz

Question

Hello there! I need to generate a Maximum length binary sequence (MLBS) with an FPGA for a project of mine, which I then have to modulate with a carrier signal. The MLBS needs to be at least 60MHz and above frequency. I found an old Spartan-3 starter kit and started working on it to try and generate such a signal. The problem is that the oscillator frequency of the board itself is just 50MHz. Hence its impossible to generate the requisite signal of 60MHz. There is a plethora of options available here and I am confused as to which will the the most cost effective board that will serve my purpose. I'd appreciate if someone guides me on to the right direction and helps me out in this regard.

Regards,

Jack

altera_forum · Answer

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I need to generate a Maximum length binary sequence (MLBS) with an FPGA for a project of mine, which I then have to modulate with a carrier signal.

--- Quote End ---

Read this:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf)

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The MLBS needs to be at least 60MHz and above frequency. I found an old Spartan-3 starter kit and started working on it to try and generate such a signal.

--- Quote End ---

This is an Altera group, not a Xilinx group, you'll have to ask for help with your board elsewhere. However, to get you started, you should use CoreGen to create a PLL, use the 50MHz as the PLL reference input, and create 60MHz as the PLL output.

Cheers,

Dave

altera_forum · Answer

Thanks a lot for that document on shift registers and Pseudo random sequences. Although I do know quite a bit about MLBS per se, the document helped me visualize the FPGA coding aspect better. Thank you for that!

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This is an Altera group, not a Xilinx group, you'll have to ask for help with your board elsewhere.

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Yes I am aware that this is an Altera group and since I know very little about Altera boards, I thought someone proficient in it could help me out in the recommendation for a suitable Altera board, if available!

The problem with using a PLL to boost the frequency is also short sighted for my project because I need to generate an MLBS of at least 60 MHz i.e. 60MHz and above until probably 120MHz. Then I also need to generate a carrier signal of say 200Mhz, modulate my MLBS onto the carrier and then get the resulting signal from an output pin. All this needs to be done on the same FPGA board thereby removing the necessity to use two different hardware for generation of the MLBS and then another for the carrier signal and their modulation.

So, can it be done???

altera_forum · Answer

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Yes I am aware that this is an Altera group and since I know very little about Altera boards, I thought someone proficient in it could help me out in the recommendation for a suitable Altera board, if available!

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There will be a suitable board ... but first lets figure out what you really want to do.

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The problem with using a PLL to boost the frequency is also short sighted for my project because I need to generate an MLBS of at least 60 MHz i.e. 60MHz and above until probably 120MHz. Then I also need to generate a carrier signal of say 200Mhz, modulate my MLBS onto the carrier and then get the resulting signal from an output pin. All this needs to be done on the same FPGA board thereby removing the necessity to use two different hardware for generation of the MLBS and then another for the carrier signal and their modulation.

So, can it be done???

--- Quote End ---

Yes, but what you need to clarify your description a little.

'Modulation' can mean two things;

1) A PRBS pattern can 'modulate' a digital data stream over a digital data link, eg., a high-speed transceiver, to ensure that data has enough transitions for the CDR at the receiver to operate in lock-to-data mode.

2) You want to multiply the PRBS sequence by an in-phase and quadrature sinusoid to generate a PRBS sequence relative to a carrier. You'd transmit that to a DAC, receive the response with an ADC, and correlate the signal looking for the peak in the response.

And I am sure there are other interpretations.

So what is it you are really trying to do? Do you need a board with ADCs/DACs?

Your statement about generating a PRBS at 60MHz and above is also ambiguous. A PRBS generates a wideband signal, so it inherently generates frequency components from 60MHz and above, in fact it generates signal from DC to infinity (multiplied by the sinc response of your output clock rate). Or did you just mean clock rate? The PLLs are programmable, so you can reconfigure the PLL from 60MHz to 120MHz dynamically, or synthesize two different designs.

Cheers,

Dave

altera_forum · Answer

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There will be a suitable board ... but first lets figure out what you really want to do.

Yes, but what you need to clarify your description a little.

'Modulation' can mean two things;

1) A PRBS pattern can 'modulate' a digital data stream over a digital data link, eg., a high-speed transceiver, to ensure that data has enough transitions for the CDR at the receiver to operate in lock-to-data mode.

2) You want to multiply the PRBS sequence by an in-phase and quadrature sinusoid to generate a PRBS sequence relative to a carrier. You'd transmit that to a DAC, receive the response with an ADC, and correlate the signal looking for the peak in the response.

And I am sure there are other interpretations.

So what is it you are really trying to do? Do you need a board with ADCs/DACs?

Your statement about generating a PRBS at 60MHz and above is also ambiguous. A PRBS generates a wideband signal, so it inherently generates frequency components from 60MHz and above, in fact it generates signal from DC to infinity (multiplied by the sinc response of your output clock rate). Or did you just mean clock rate? The PLLs are programmable, so you can reconfigure the PLL from 60MHz to 120MHz dynamically, or synthesize two different designs.

Cheers,

Dave

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Phew!!! This is exactly what I was waiting for! Thanks a lot for that thorough information. I'm sorry if I sounded ambiguous. Its partly because I am quite a newbie when it come to asking questions in a forum and partly because I still am not completely well versed (as you may have probably understood by now) with the actual programming of FPGAs. Its still work in progress.

Now to answer your questions...

In my case 'Modulation' means exactly what you've explained in case 2. I need to generate an MLBS relative to the sinusiod carrier and later on get the peak in the response of the correlated signal.

I do not need an ADC/DAC at the moment. I'm gonna build that externally and interface it accordingly. At least thats what I am planning of at the moment.

Also, I need the clock frequency of at least 60MHz and above. I am aware of the theory of an MLBS signal and am aware of the complete spreading property of the signal. Sorry if I mislead you there as well.

Also, I have worked on 8 and 32 bit microcontrollers before and have used the PLLs to pull up the frequency of the oscillator clock to the required frequency but I haven't done so in an FPGA. Is it similar or is there another way to do the same?

Thanks for your patience in explaining the concepts to me. Kindly excuse my naivete in the matter!

Regards,

Jack

altera_forum · Answer

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In my case 'Modulation' means exactly what you've explained in case 2. I need to generate an MLBS relative to the sinusiod carrier and later on get the peak in the response of the correlated signal.

--- Quote End ---

What is the bandwidth of the signal you are transmitting? What are the out-of-band rejection requirements?

Here's what you will need to do;

1) Generate a PRBS sequence.

2) Use an interpolation filter to increase the effective sample rate, and produce the bandpass signal you hope to transmit.

3) Send the data to the transmit DAC for possibly further interpolation and inverse-sinc correction, and then conversion to analog.

--- Quote Start ---

I do not need an ADC/DAC at the moment. I'm gonna build that externally and interface it accordingly. At least thats what I am planning of at the moment.

--- Quote End ---

You need to decide on your ADC/DAC now so that you know what logic will be in your FPGA.

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Also, I need the clock frequency of at least 60MHz and above. I am aware of the theory of an MLBS signal and am aware of the complete spreading property of the signal. Sorry if I mislead you there as well.

--- Quote End ---

You need to understand that the PRBS has wider bandwidth than you can transmit, or will be allowed to transmit. So given that understanding, what are you allowed to transmit?

--- Quote Start ---

Also, I have worked on 8 and 32 bit microcontrollers before and have used the PLLs to pull up the frequency of the oscillator clock to the required frequency but I haven't done so in an FPGA. Is it similar or is there another way to do the same?

--- Quote End ---

FPGAs have PLLs. Your FPGA board will need to have an external low-jitter oscillator and possible external PLLs that route to the ADC and DAC. You would not generate those from the FPGA internal PLLs. The FPGA will be clocked by the low-jitter oscillator directly, and then its PLL can be used to create a clock that is phase-locked to the same frequency as the DAC/ADC. The DAC/ADC will likely generate clocks to the FPGA used for synchronous data transfer. Dual-clock FIFOs would be used to transfer data from the FPGA PLL clock domain into the ADC and DAC clock domains (which are the same frequency, but have different phase shifts).

Inside your FPGA, you will have;

1) Transmitter logic; your PRBS generator, your filter, and a numerically controlled oscillator to generate a bandpass noise sequence modulated around a carrier (not necessarily your final carrier, since the DAC can do that, depending on the device you select).

2) Receiver logic; a digital downconversion, low-pass filter, and decimation stage, followed by correlation to find the peak of your signal.

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Thanks for your patience in explaining the concepts to me. Kindly excuse my naivete in the matter!

--- Quote End ---

Read these documents, they should help ...

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip)

Cheers,

Dave

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Board recommendation for MLBS until 60MHz

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