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I need to generate a Maximum length binary sequence (MLBS) with an FPGA for a project of mine, which I then have to modulate with a carrier signal.
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Read this:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf)
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The MLBS needs to be at least 60MHz and above frequency. I found an old Spartan-3 starter kit and started working on it to try and generate such a signal.
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This is an Altera group, not a Xilinx group, you'll have to ask for help with your board elsewhere. However, to get you started, you should use CoreGen to create a PLL, use the 50MHz as the PLL reference input, and create 60MHz as the PLL output.
Cheers,
Dave
Honored Contributor
