--- Quote Start ---
In my case 'Modulation' means exactly what you've explained in case 2. I need to generate an MLBS relative to the sinusiod carrier and later on get the peak in the response of the correlated signal.
--- Quote End ---
What is the bandwidth of the signal you are transmitting? What are the out-of-band rejection requirements?
Here's what you will need to do;
1) Generate a PRBS sequence.
2) Use an interpolation filter to increase the effective sample rate, and produce the bandpass signal you hope to transmit.
3) Send the data to the transmit DAC for possibly further interpolation and inverse-sinc correction, and then conversion to analog.
--- Quote Start ---
I do not need an ADC/DAC at the moment. I'm gonna build that externally and interface it accordingly. At least thats what I am planning of at the moment.
--- Quote End ---
You need to decide on your ADC/DAC now so that you know what logic will be in your FPGA.
--- Quote Start ---
Also, I need the clock frequency of at least 60MHz and above. I am aware of the theory of an MLBS signal and am aware of the complete spreading property of the signal. Sorry if I mislead you there as well.
--- Quote End ---
You need to understand that the PRBS has wider bandwidth than you can transmit, or will be allowed to transmit. So given that understanding, what are you allowed to transmit?
--- Quote Start ---
Also, I have worked on 8 and 32 bit microcontrollers before and have used the PLLs to pull up the frequency of the oscillator clock to the required frequency but I haven't done so in an FPGA. Is it similar or is there another way to do the same?
--- Quote End ---
FPGAs have PLLs. Your FPGA board will need to have an external low-jitter oscillator and possible external PLLs that route to the ADC and DAC. You would not generate those from the FPGA internal PLLs. The FPGA will be clocked by the low-jitter oscillator directly, and then its PLL can be used to create a clock that is phase-locked to the same frequency as the DAC/ADC. The DAC/ADC will likely generate clocks to the FPGA used for synchronous data transfer. Dual-clock FIFOs would be used to transfer data from the FPGA PLL clock domain into the ADC and DAC clock domains (which are the same frequency, but have different phase shifts).
Inside your FPGA, you will have;
1) Transmitter logic; your PRBS generator, your filter, and a numerically controlled oscillator to generate a bandpass noise sequence modulated around a carrier (not necessarily your final carrier, since the DAC can do that, depending on the device you select).
2) Receiver logic; a digital downconversion, low-pass filter, and decimation stage, followed by correlation to find the peak of your signal.
--- Quote Start ---
Thanks for your patience in explaining the concepts to me. Kindly excuse my naivete in the matter!
--- Quote End ---
Read these documents, they should help ...
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip)
Cheers,
Dave
Honored Contributor
