Asynch Design Challenge

I can do it with two sync reset DFFs, a toggle FF and a 2 input AND gate which I think should fit in 3 LEs.

reg r1, r2, clkout:
always @ (posedge clkin)
  begin
     if (reset)
             begin
           r1 <= 1'b0;
           r2 <= 1'b0;
           clkout <= 1'b0;
       end
     else if (r1 & r2)
       begin
          r1 <= 1'b0;
          r2 <= 1'b0;
          clkout <= ~clkout;       
       end
    else 
      begin
         r1 <= 1'b1;
         r2 <= r1;
     end
end

It's a serial topic in electronic forums (and in job interviews, too). You can e.g. search edaboard.com for "divide by 3".

I am afraid Cris72 that your code doesn't appear to work. I would also guess that the mark to space won't be that good either once corrected (though probably good enough for most people).

module divider3
  (
  reset,
  clkin,
  clkout
  );
 
input reset; 
input clkin;
output clkout;
reg r1, r2, clkout;
always @ (posedge clkin or negedge clkin)
  begin
     if (reset)
       begin
           r1 <= 1'b0;
           r2 <= 1'b0;
           clkout <= 1'b0;
       end
     else if (r1 & r2)
       begin
          r1 <= 1'b0;
          r2 <= 1'b0;
          clkout <= ~clkout;
       end
    else 
      begin
         r1 <= 1'b1;
         r2 <= r1;
      end
  end
endmodule

Cris72, are you compiling that in ModelSim or Quartus 2? Within Quartus 2 I'm getting the following:

I'm always up for fun. It so happens I've never done this one before. How about this. It results in 2 ALUTs and 2 Registers.

module div_by_3(
  input         clkin,
  output  reg   clkout
);
wire  rstn;
reg   clkout_r;
wire  clkout_r_n;
assign  clkout_r_n = ~clkout_r;
assign  rstn = clkout_r_n | clkin;
always @(posedge clkin or negedge rstn)
  if(~rstn) clkout  <= 1'b0;
  else      clkout  <= clkout_r_n;
always @(posedge clkin)
          clkout_r  <= clkout;
initial begin
  clkout    = 1'b0;
  clkout_r  = 1'b0;
end
endmodule

It looks good. 2 LEs (according to Quartus way of counting resources) can't be beaten.

2 LEs is good. I didn't think that would have been possible but you have proven me wrong. I'd post my design but I've a PC power supply failure to work around at the moment which is a pain.