Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAsynch Design Challenge
After all the chat in this thread (http://www.alteraforum.com/forum/showthread.php?t=26151)regarding glitching in the outputs of asynchronous logic, I thought I would post the following challenge fo...
Altera_ForumHonored Contributor
Honored ContributorI can do it with two sync reset DFFs, a toggle FF and a 2 input AND gate which I think should fit in 3 LEs.
The following pseudo code shows how I connect the above stuff.
reg r1, r2, clkout:
always @ (posedge clkin)
begin
if (reset)
begin
r1 <= 1'b0;
r2 <= 1'b0;
clkout <= 1'b0;
end
else if (r1 & r2)
begin
r1 <= 1'b0;
r2 <= 1'b0;
clkout <= ~clkout;
end
else
begin
r1 <= 1'b1;
r2 <= r1;
end
end
