Asynch Design Challenge

Cris72, are you compiling that in ModelSim or Quartus 2? Within Quartus 2 I'm getting the following:

Error (10239): Verilog HDL Always Construct error at asynchclockdiv.v(21): event control cannot test for both positive and negative edges of variable "clkin"

line 21 is "always @ (posedge clkin or negedge clkin)"

If you can trigger off both edges of the clock then the design of a div 3 is trivial. However, this isn't something you can easily do in Altera FPGAs. (at least that is my understanding).

You are right though about the mark to space, I wasn't looking carefully enough at how your code worked.