Asynch Design Challenge

I'm always up for fun. It so happens I've never done this one before. How about this. It results in 2 ALUTs and 2 Registers.

module div_by_3(
  input         clkin,
  output  reg   clkout
);
wire  rstn;
reg   clkout_r;
wire  clkout_r_n;
assign  clkout_r_n = ~clkout_r;
assign  rstn = clkout_r_n | clkin;
always @(posedge clkin or negedge rstn)
  if(~rstn) clkout  <= 1'b0;
  else      clkout  <= clkout_r_n;
always @(posedge clkin)
          clkout_r  <= clkout;
initial begin
  clkout    = 1'b0;
  clkout_r  = 1'b0;
end
endmodule