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Altera_Forum's avatar
Altera_Forum
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10 years ago

ALTLVDS external clock

Hi all,

I'm trying to implement the ALTLVDS_RX in a cyclone V.

i would to connect the rx_enable and the rx_inclock to a fpga i/o (lvds dedicate input clock pins).

is it possible?

For now I'm stuck to the error:

"error: ir fifo userdes block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:altlvds_rx_component|lvds_rx_lvds_rx:auto_generated|sd2' is not properly connected on the 'writeclk' port.

it must be connected to one of the valid ports listed below.

info: can be connected to loaden port of arriav_pll_lvds_output wysiwyg

info: can be connected to outclk port of generic_pll wysiwyg

info: can be connected to lvdsclk port of cyclonev_pll_lvds_output wysiwyg info: can be connected to outclk port of arriav_clkena wysiwyg (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd02152013_340.html)"

If I use the relate solution (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04102013_389.html), my quartus crash during the synthesis.

I think that the primitive cyclonev_pll_lvds_output needs a pll, but I have not a pll before the ALTLVDS_RX.

So, the question is:

can i use an altlvds_rx without pll?

Thank you.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    There is a parameter editor allow you to choose the "Use External PLL option".

    You can refer to the ALTLVDS IP core in external PLL mode from LVDS user guide for more details.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi all,

    dear ah_zhi02,

    when you talk about "the external clock chapter" are you referring to "ALTLVDS IP Core in External PLL Mode" p. 62?

    I have not found an external clock chapter and the guidelines p 62 are for the external pll. I don't want to use any pll. All my clocks are generated externally to the FPGA.

    dear irish,

    I'm already using the External PLL option but the clock that I want to use are coming from a FPGA pin. They are not coming from a pll.

    dear nicejob,

    I have already used the solution https://www.altera.com/support/suppo...02013_389.html. The problem is that I think that the primitive cyclonev_pll_lvds_output needs a pll, but I have not a pll before the ALTLVDS_RX.

    When I use a cyclonev_pll_lvds_output my quartus crash during the synthesis.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    The clock must come from a PLL. These are dedicated paths laid out for minimal skew/max performance. This allows the dedicated LVDS circuitry to run at a much higher rate, although it loses some flexibility.

    (There are three outputs from the PLL that must be in sync with each other, the high-speed clock, the low-speed clock, and the load enable signal. I'm not sure how you're planning on doing this without a PLL).