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Honored Contributor
Honored ContributorALTLVDS external clock
Hi all, I'm trying to implement the ALTLVDS_RX in a cyclone V. i would to connect the rx_enable and the rx_inclock to a fpga i/o (lvds dedicate input clock pins). is it possible? For now ...
Altera_ForumHonored Contributor
Honored ContributorHi all,
dear ah_zhi02, when you talk about "the external clock chapter" are you referring to "ALTLVDS IP Core in External PLL Mode" p. 62? I have not found an external clock chapter and the guidelines p 62 are for the external pll. I don't want to use any pll. All my clocks are generated externally to the FPGA. dear irish, I'm already using the External PLL option but the clock that I want to use are coming from a FPGA pin. They are not coming from a pll. dear nicejob, I have already used the solution https://www.altera.com/support/suppo...02013_389.html. The problem is that I think that the primitive cyclonev_pll_lvds_output needs a pll, but I have not a pll before the ALTLVDS_RX. When I use a cyclonev_pll_lvds_output my quartus crash during the synthesis.
