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Honored Contributor
Honored ContributorALTLVDS external clock
Hi all, I'm trying to implement the ALTLVDS_RX in a cyclone V. i would to connect the rx_enable and the rx_inclock to a fpga i/o (lvds dedicate input clock pins). is it possible? For now ...
Altera_ForumHonored Contributor
Honored ContributorThe clock must come from a PLL. These are dedicated paths laid out for minimal skew/max performance. This allows the dedicated LVDS circuitry to run at a much higher rate, although it loses some flexibility.
(There are three outputs from the PLL that must be in sync with each other, the high-speed clock, the low-speed clock, and the load enable signal. I'm not sure how you're planning on doing this without a PLL).
