Adding and resizing in one step

If your tool understands and supports the following:

sum = (num1 + num2)/2**4;

Then it is equivalent to discarding 4 bits from result unless it goes silly and creates a division module.

alternatively if you can accept truncation errors then:

sum <= num1(6 downto 4) + num2(6 downto 4);

is almost equivalent but division is done on operands.

Thanks kaz for your reply!

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sum = (num1 + num2)/2**4;

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I guess that in this case sum must have the same size as num1 and num2? I would rather have that sum already has the smaller size.

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alternatively if you can accept truncation errors then:

sum <= num1(6 downto 4) + num2(6 downto 4);

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I think I will go with this one.

If there would be a way to avoid truncation errors, please let me know.

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If there would be a way to avoid truncation errors, please let me know.

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Yes. The code you origionall posted:

temp <= number1 + number2

sum <= temp(7 downto 4)

I forget if VHDL has a right shift operator but if it does you could use that to take the 8 bit value and only assign the upper 4 bits to the destination.

What Tricky said is how I typically do this in verilog even though >> would get the job done.

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Hi,

Is there a way to add two unsigned numbers and extract only the x most significant bits from it in one step?

I want something like this:

sum <= resize(number1 + number2,4)

Instead of:

temp <= number1 + number2

sum <= temp(7 downto 4)

The existing resize function in numeric_std drops the msb's, I want the lsb's dropped.

Thanks in advance!

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assuming you are using type 'unsigned'

sum <= to_unsigned( (to_integer(number1)+to_integer(number2)) / 16 , 4) ;

but this works even nicer :

sum <= unsigned( number21 + number22 )(7 downto 4) ;

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but this works even nicer :

sum <= unsigned( number21 + number22 )(7 downto 4) ;

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I have two problems with this construct

- it doesn't refer to a defined VHDL syntax as far as I'm aware of

- it leaves sum unconnected in Quartus V9.0, without generating an error

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I have two problems with this construct

- it doesn't refer to a defined VHDL syntax as far as I'm aware of

- it leaves sum unconnected in Quartus V9.0, without generating an error

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I verified it in 12.0 in the RTL-viewer. Both constructs generated the same 'schematic'. I almost sure it will also work in 9.1 as I have used similar constructs in 9.1-based projects.

I have never looked at the offical VHDL specification and I am not a language expert but let's elaborate:

if we write

sum <= n1 + n2 ;

we conclude that the sum of the two unsigned vectors is assigned to an unsigned vector. The VHDL compiler knows how to do this. Internally the compiler may represent the result of 'n1 + n2' in any format it thinks suited, but it will convert it into the unsigned representation of the LHS.

Now consider a function

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func( par : xxx) return unsigned ...

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we can do the following:

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sum <= func( n1 + n2 )

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assuming func handles the type of 'n1 + n2'.

A function returns an (RHS) object of the specified type and as such we can write the following:

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sum <= func(n1 + n2)(7 downto 4) ;

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A typecast is a kind of special function, so we can replace the function func() with the typecast unsigned() resulting in

sum <= unsigned(n1 + n2)(7 downto 4) ;

So we can save some typing and can do with less 'intermediate' signals cluttering up the file.

It also works with the dot-operator for functions returning a record type.

You may have to enable VHDL 2008 support, I always do ...

I see, that the construct (slice of a type conversion function) is supported in Quartus 12, with or without VHDL 2008 activation.

In Quartus V9.0, the expression is accepted without throwing an error, but doesn't assign a value to the LHS. A slice of a regular function call works in Quartus 9.

I don't think that the slice of a type conversion function is a VHDL 2008 feature. It's something that you can read into the general properties of a "globally static primary", although I never found it mentioned in literature.

Thanks for suggesting the interesting construct.