Forum Discussion
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- but this works even nicer : sum <= unsigned( number21 + number22 )(7 downto 4) ; --- Quote End --- I have two problems with this construct - it doesn't refer to a defined VHDL syntax as far as I'm aware of - it leaves sum unconnected in Quartus V9.0, without generating an error