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Honored ContributorADC output from LVDS deserializer.
Hi,
I have a an ADC sampling at 40 MHz, and it output LVDS signal, so i have to deserialize it using my DE2-115, but i am having trouble with the deserialized signal (shown in the picture), it should display a pure sine wave. I have no idea what are the possible solution. I am using the lvds_rx block provided from megawizard. I have not set the .SDC file yet, you think that might solve the problem? Please comment.. regards, Michael33 Replies
Altera_Forumsince the noise you have on your signal is not diffuse I suspect it not analogue but is due to fpga io or timing inside. You can see that most of the error is due to bit 11 ringing and one or so other bits.
- Altera_Forum
I agree that the problem is probably timing issue.
So, how should i define the timing constraint in .SDC ? and how is it going to help solving the problem? Michael - Altera_Forum
you will need your sdc certainly and a word of caution about the way you sample your signaltap, use the same data clock
- Altera_Forum
you need to enter your clock and check the tCO of your ADC device and then use set input constraints accordingly for tSU and tH. see examples
in altera website, timequest design centre - Altera_Forum--- Quote Start --- you will need your sdc certainly and a word of caution about the way you sample your signaltap, use the same data clock --- Quote End --- IIUC, by data clock, you mean the frame clock (slow clock) of LVDS ? --- Quote Start --- you need to enter your clock and check the tCO of your ADC device and then use set input constraints accordingly for tSU and tH. see examples in altera website, timequest design centre --- Quote End --- Thank you very much KAZ! i will try according to your advice.! Michael
- Altera_Forum
I am not familiar with your particular setup as ADCs come with various formats. If you mean you deserialise your ADC raw data arriving at 40 M bits per sec then the data clock is that of 40/12 (frame clock if that is what you mean by frame clock). Do not divide the clock through logic as that will cause timing problems.
When you write first sdc you will be possibly swearing at altera but focus on clock entry and set input delay. - Altera_Forum--- Quote Start --- When you write first sdc you will be possibly swearing at altera but focus on clock entry and set input delay. --- Quote End --- Oh.. yea!... i thought timing constraint stuffs were done automatically, since i inputted the clock speed, input data rate in Megawizard, so i thought Quartus 2 is smart enough to extract required information from these wizard generated files.
- Altera_Forum
Are sure, that the receiver clock phase has been set correctly according to the ADC timing?
- Altera_Forum--- Quote Start --- Are sure, that the receiver clock phase has been set correctly according to the ADC timing? --- Quote End --- I am sure i did not do that. and How do i do that?? Attached is the output timing characteristic of my ADC (i want it to run at 40MHz) so far, i have this in my .SDC create_clock -period 4.15 [get_ports HSMC_CLKIN_P2] # this is because the input of LVDS is at 240 MHz, due to (40MHz*12bits/2 = 240MHz)i guess... derive_pll_clocks derive_clock_uncertainty set_input_delay -clock HSMC_CLKIN_P2 -max .61 [all_inputs] set_input_delay -clock HSMC_CLKIN_P2 -min 0.55 [all_inputs] I am sure these are wrong, cause the shape of sine wave reconstructed is worst. Michael
- Altera_Forum
Your sdc looks ok to me. Check report if you indeed got that.
You will also need lvds termination, go to project settings (assignment editor). If it is DDR, you will need constraints for both edges. You can also try rotate the PLL clock if you are using pll if you can't pass timing. Moreover, it could be timing not at io but at point when you sample the data on to 40MHz. Note 40MHs clock is edge aligned with data and you better do some shift away from edge e.g sample on opposite edge.
