ADC output from LVDS deserializer.

Your sdc looks ok to me. Check report if you indeed got that.

You will also need lvds termination, go to project settings (assignment editor).

If it is DDR, you will need constraints for both edges.

You can also try rotate the PLL clock if you are using pll if you can't pass timing.

Moreover, it could be timing not at io but at point when you sample the data on to 40MHz. Note 40MHs clock is edge aligned with data and you better do some shift away from edge e.g sample on opposite edge.