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Are sure, that the receiver clock phase has been set correctly according to the ADC timing?
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I am sure i did not do that.
and How do i do that??
Attached is the output timing characteristic of my ADC (i want it to run at 40MHz)
so far, i have this in my .SDC
create_clock -period 4.15 [get_ports HSMC_CLKIN_P2] # this is because the input of LVDS is at 240 MHz, due to (40MHz*12bits/2 = 240MHz)i guess...
derive_pll_clocks
derive_clock_uncertainty
set_input_delay -clock HSMC_CLKIN_P2 -max .61 [all_inputs]
set_input_delay -clock HSMC_CLKIN_P2 -min 0.55 [all_inputs]
I am sure these are wrong, cause the shape of sine wave reconstructed is worst.
Michael
Honored Contributor
