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Honored Contributor
Honored ContributorADC output from LVDS deserializer.
Hi, I have a an ADC sampling at 40 MHz, and it output LVDS signal, so i have to deserialize it using my DE2-115, but i am having trouble with the deserialized signal (shown in the picture), it ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- When you write first sdc you will be possibly swearing at altera but focus on clock entry and set input delay. --- Quote End --- Oh.. yea!... i thought timing constraint stuffs were done automatically, since i inputted the clock speed, input data rate in Megawizard, so i thought Quartus 2 is smart enough to extract required information from these wizard generated files.
