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Altera_Forum's avatar
Altera_Forum
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14 years ago

ADC output from LVDS deserializer.

Hi, I have a an ADC sampling at 40 MHz, and it output LVDS signal, so i have to deserialize it using my DE2-115, but i am having trouble with the deserialized signal (shown in the picture), it ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I am not familiar with your particular setup as ADCs come with various formats. If you mean you deserialise your ADC raw data arriving at 40 M bits per sec then the data clock is that of 40/12 (frame clock if that is what you mean by frame clock). Do not divide the clock through logic as that will cause timing problems.

When you write first sdc you will be possibly swearing at altera but focus on clock entry and set input delay.