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Anonymous's avatar
Anonymous
2 years ago

Verilog Coding

I am getting the following error
[Synth 8-403] loop limit (65536) exceeded

Could somebody please help, the design code is as below:

module latchregister_4bit(
input clk, reset,
input in,
output reg pulse,
output [3:0]out);

parameter DUTY = 50; // in percentage
parameter clk_pd = 10;
parameter clk_on = (DUTY * clk_pd) / 100;
parameter clk_off = (100 - DUTY) * clk_pd / 100;

reg start_clk;

// Initialize variables to zero
initial
begin
start_clk <= 0;
pulse <= 0;
end

always@(posedge clk or negedge clk) begin
if(clk)
start_clk = 1;
else
start_clk = 0;
end

// Achieve duty cycle by a skewed clock on/off
// run as long as the clocks are turned on.
always@(posedge start_clk) begin
if (start_clk) begin
pulse = 1;
while (start_clk) begin
#(clk_on) pulse = 0;
#(clk_off) pulse = 1;
end
pulse = 0;
end
end

reg [3:0]q;
always@(pulse)
begin
if(reset)
q<=4'b0000;
else if(pulse)
q<={in,q[3:1]};
end

assign out = q;
endmodule

Board Debug
Fpga Devkit

4 Replies

  • _AK6DN_'s avatar
    _AK6DN_
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Getting an error from what tool? Quartus? Modelsim? Or what?

    Are you trying to just simulate some verilog code or trying to compile/synthesize for a device? If so, what device?

    FYI your code may be legal verilog syntax so a simulator may accept it, but it is not synthesizeable verilog.

    Structures like this:

    pulse = 1;
while (start_clk) begin
    #(clk_on) pulse = 0;
    #(clk_off) pulse = 1;
    end
pulse = 0;

    are not valid synthesis structures.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Hi,
    you have written a potentially endless loop statement. Basically it's a misunderstanding about the purpose of loop statements in synthesized Verilog. They are used to generate parallel logic rather than a sequence in time.
  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi,


    while (start_clk) begin

    #(clk_on) pulse = 0;

    #(clk_off) pulse = 1;

    end

    This part causes the loop doesn't have any way to exit, it becomes an infinite loop that the synthesis tool cannot handle. May be you can use a counter to count the number of clock cycles for the on and off periods to achieve the duty cycle you're looking for.


    Thanks,

    Best Regards,

    Sheng