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Verilog Coding
I am getting the following error [Synth 8-403] loop limit (65536) exceeded Could somebody please help, the design code is as below: module latchregister_4bit( input clk, reset, input in, o...
FvM
Super Contributor
Super ContributorHi,
you have written a potentially endless loop statement. Basically it's a misunderstanding about the purpose of loop statements in synthesized Verilog. They are used to generate parallel logic rather than a sequence in time.
you have written a potentially endless loop statement. Basically it's a misunderstanding about the purpose of loop statements in synthesized Verilog. They are used to generate parallel logic rather than a sequence in time.
