Verilog Coding
I am getting the following error [Synth 8-403] loop limit (65536) exceeded Could somebody please help, the design code is as below: module latchregister_4bit( input clk, reset, input in, o...
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ShengN_altera
Super Contributor
Super ContributorHi,
while (start_clk) begin
#(clk_on) pulse = 0;
#(clk_off) pulse = 1;
end
This part causes the loop doesn't have any way to exit, it becomes an infinite loop that the synthesis tool cannot handle. May be you can use a counter to count the number of clock cycles for the on and off periods to achieve the duty cycle you're looking for.
Thanks,
Best Regards,
Sheng
