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Anonymous's avatar
Anonymous
Not applicable
3 years ago

Verilog Coding

I am getting the following error [Synth 8-403] loop limit (65536) exceeded Could somebody please help, the design code is as below: module latchregister_4bit( input clk, reset, input in, o...
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Fpga Devkit
_AK6DN_'s avatar
_AK6DN_
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3 years ago

Getting an error from what tool? Quartus? Modelsim? Or what?

Are you trying to just simulate some verilog code or trying to compile/synthesize for a device? If so, what device?

FYI your code may be legal verilog syntax so a simulator may accept it, but it is not synthesizeable verilog.

Structures like this:

pulse = 1;
while (start_clk) begin
    #(clk_on) pulse = 0;
    #(clk_off) pulse = 1;
    end
pulse = 0;

are not valid synthesis structures.