Triple speed ethernet and Marvell Phy on Stratix III

First you need to check that the PHY didn't auto-negotiate a 1Gbs link. Because in that case if you try to use the MII interface it won't work.

Then you can add some Signal Tap probes to see what signals are coming from the PHY it should help you understand why the MAC doesn't process them.

Thanks for the reply.

I was connecting the ethernet cable into 10/100 router and i gounded set_1000 to make sure it's not running on Gigabit. Also i checked the LED indicator with the right ethernet mode indication.

For the Signal Tap, I will try it right away.

BTW, i happened to see some threads mentioning about timing constraints on TSE_MAC related signals. Do you think that's very likely apply in my case. I believe I didn't touch that at all..:(

Hi.. Help!!

I've tried to do the time constaints on all tse_mac related signals (following tse_mac_constraints.sdc) and i can get the report of the time request without any negative slack in all models.

However, after i loaded the image on the board, it's still about the same thing. In 10/100 mode (GMII/MII), only RX LED is on, and never see TX LED lit.

I also tried RGMII mode, and followed the timing scripts you mentioned in the other thread. Fortunetely, i can see both RX and TX LED lit. However, the data still can't get through.. (but i think its situation is better than MII mode)

So my question is do i have to follow that sample timing scripts which you provide (like chaning 125MHz to 25MHz for Ethernet 100 mode)?

Or i miss something here?

(maybe i should have Marvell PHy spec and follow its recommendaton for the time constraints)

BTW, the timing script:# **************************************************************# Create Clock#**************************************************************create_clock -name {clkin_125} -period 8 [get_ports {clkin_125}]create_clock -name {enet_rx_clk} -period 8 [get_ports {enet_rx_clk}]#**************************************************************# Create Generated Clock#**************************************************************derive_pll_clocksset enet_tx_in_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk[0]set enet_tx_out_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk[1]#**************************************************************# Set Input Delay#**************************************************************set_input_delay -clock enet_rx_clk -min 1.5 [get_ports {enet_rxd

[*] enet_rx_dv}] -add_delayset_input_delay -clock enet_rx_clk -max 2.5 [get_ports {enet_rxd

[*] enet_rx_dv}] -add_delayset_input_delay -clock enet_rx_clk -clock_fall -min 1.5 [get_ports {enet_rxd

[*] enet_rx_dv}] -add_delayset_input_delay -clock enet_rx_clk -clock_fall -max 2.5 [get_ports {enet_rxd

[*] enet_rx_dv}] -add_delay#**************************************************************# Set Output Delay#**************************************************************set_output_delay -clock $enet_tx_out_clk -max 1 [get_ports {enet_txd

[*] enet_tx_en}]set_output_delay -clock $enet_tx_out_clk -min -1 [get_ports {enet_txd

[*] enet_tx_en}] -add_delayset_output_delay -clock $enet_tx_out_clk -clock_fall -max 1 [get_ports {enet_txd

[*] enet_tx_en}] -add_delayset_output_delay -clock $enet_tx_out_clk -clock_fall -min -1 [get_ports {enet_txd

[*] enet_tx_en}] -add_delay#**************************************************************# Set Clock Groups#**************************************************************set_clock_groups -exclusive -group [get_clocks {clkin_125 enet_tx_in_clk enet_tx_out_clk}] set_clock_groups -exclusive -group [get_clocks {enet_rx_clk}]# **************************************************************# Set False Path#**************************************************************set_false_path -from [get_ports {enet_mdio}]set_false_path -to [get_ports {enet_mdc enet_mdio}]set_false_path -setup -rise_from $enet_tx_in_clk -fall_to $enet_tx_out_clkset_false_path -setup -fall_from $enet_tx_in_clk -rise_to $enet_tx_out_clkset_false_path -hold -rise_from $enet_tx_in_clk -rise_to $enet_tx_out_clkset_false_path -hold -fall_from $enet_tx_in_clk -fall_to $enet_tx_out_clk#**************************************************************# Set Multicycle Path#**************************************************************set_multicycle_path -from $enet_tx_in_clk -to $enet_tx_out_clk -setup -start 2#**************************************************************# Set Maximum Delay#**************************************************************set_max_delay -from $enet_tx_out_clk -to [get_ports {enet_gtx_clk}] 20#**************************************************************# Set Minimum Delay#**************************************************************set_min_delay -from $enet_tx_out_clk -to [get_ports {enet_gtx_clk}] 0

IIRC the Altera TSE mac doesn't work very well with RGMII at 10/100 speeds, so you should stick to MII. The constraints will need some adjustments as you are not in DDR anymore.

Did you try to connect SignalTap probes to the MII signals to check if anything is received on that side?

Hi.. Daixiwen,

Thanks for your reminding again.

I use SignalTap to check the signals and found out that enet_rx_clk and enet_tx_clk were not moving at all.. I think that's the reason i didn't see any rx data or tx data.

However, what's the reason to make them like this?

Since i can talk to PHY through MDIO.. is that my design problem?

Just don't understand why..

I follow almost everything from the standard example of cyclone III.

Can you give me some suggestions?

BTW i attached the start up log here for simple socket server.

Thanks again for your help.

******************************************************

nios2-terminal: connected to hardware target using JTAG UART on cable

nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)

=============== Software License Reminder ================

This software project uses an unlicensed version of the NicheStack TCP/IP

Network Stack - Nios II Edition. If you want to ship resulting object

code in your product, you must purchase a license for this software from

Altera. For information go to: "http://www.altera.com/nichestack"

=====================================================

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2007 by InterNiche Technologies. All rights reserved.

prep_tse_mac 0

Your Ethernet MAC address is 00:07:ed:ff:49:00

prepped 1 interface, initializing...

[tse_mac_init]

SGDMA desc memory cleared

INFO : TSE MAC 0 found at address 0x00001c00

INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0]

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : Applying additional PHY configuration of Marvell 88E1111

INFO : PHY[0.0] - Checking link...

INFO : PHY[0.0] - Link established

INFO : PHY[0.0] - Gigabit = 0, Duplex = Full

OK, x=0, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x04000203

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

IP address of et1 : 192.168.50.234

Created "Inet main" task (Prio: 2)

Created "clock tick" task (Prio: 3)

DHCP timed out, going back to default IP address(es)

Simple Socket Server starting up

[sss_task] Simple Socket Server listening on port 30

Created "simple socket server" task (Prio: 4)

Can you post your top level HDL file? We might be able to quickly determine if you've got something wrong.

Also, as a first step, I would recommend double-checking all of your pin assignments that connect to the MAC.

Is this a custom board or are you using a development kit?

Jake

The ethernet tx clk comes from the PHY when using MII, or comes from the FPGA when using GMII. So in your case both rx and tx clocks should be inputs.

Did you double check the assignments for these two pins? Are they inputs, with the correct I/O standard? Are they connected to the correct pins of the PHY on your board?

Yup.. I have double-checked the pin assignment and they matched exactly the same as shown in reference manual of Stratix III.

Also i don't need to make any changes on pin assignment because i use the standard example from Stratix III. It's there from the beginning.

BTW, I'm wondering about that wierd reset issue with on-board Marvell PHY.. For this reset circuitry, i was following an example posted on this forum, however i checked its delay between user_resetn and enet_resetn is quite long according to his design.. Could this be an issue here?