Triple speed ethernet and Marvell Phy on Stratix III

Hi.. Help!!

I've tried to do the time constaints on all tse_mac related signals (following tse_mac_constraints.sdc) and i can get the report of the time request without any negative slack in all models.

However, after i loaded the image on the board, it's still about the same thing. In 10/100 mode (GMII/MII), only RX LED is on, and never see TX LED lit.

I also tried RGMII mode, and followed the timing scripts you mentioned in the other thread. Fortunetely, i can see both RX and TX LED lit. However, the data still can't get through.. (but i think its situation is better than MII mode)

So my question is do i have to follow that sample timing scripts which you provide (like chaning 125MHz to 25MHz for Ethernet 100 mode)?

Or i miss something here?

(maybe i should have Marvell PHy spec and follow its recommendaton for the time constraints)

BTW, the timing script:# **************************************************************# Create Clock#**************************************************************create_clock -name {clkin_125} -period 8 [get_ports {clkin_125}]create_clock -name {enet_rx_clk} -period 8 [get_ports {enet_rx_clk}]#**************************************************************# Create Generated Clock#**************************************************************derive_pll_clocksset enet_tx_in_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk[0]set enet_tx_out_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk[1]#**************************************************************# Set Input Delay#**************************************************************set_input_delay -clock enet_rx_clk -min 1.5 [get_ports {enet_rxd

[*] enet_rx_dv}] -add_delayset_input_delay -clock enet_rx_clk -max 2.5 [get_ports {enet_rxd

[*] enet_rx_dv}] -add_delayset_input_delay -clock enet_rx_clk -clock_fall -min 1.5 [get_ports {enet_rxd

[*] enet_rx_dv}] -add_delayset_input_delay -clock enet_rx_clk -clock_fall -max 2.5 [get_ports {enet_rxd

[*] enet_rx_dv}] -add_delay#**************************************************************# Set Output Delay#**************************************************************set_output_delay -clock $enet_tx_out_clk -max 1 [get_ports {enet_txd

[*] enet_tx_en}]set_output_delay -clock $enet_tx_out_clk -min -1 [get_ports {enet_txd

[*] enet_tx_en}] -add_delayset_output_delay -clock $enet_tx_out_clk -clock_fall -max 1 [get_ports {enet_txd

[*] enet_tx_en}] -add_delayset_output_delay -clock $enet_tx_out_clk -clock_fall -min -1 [get_ports {enet_txd

[*] enet_tx_en}] -add_delay#**************************************************************# Set Clock Groups#**************************************************************set_clock_groups -exclusive -group [get_clocks {clkin_125 enet_tx_in_clk enet_tx_out_clk}] set_clock_groups -exclusive -group [get_clocks {enet_rx_clk}]# **************************************************************# Set False Path#**************************************************************set_false_path -from [get_ports {enet_mdio}]set_false_path -to [get_ports {enet_mdc enet_mdio}]set_false_path -setup -rise_from $enet_tx_in_clk -fall_to $enet_tx_out_clkset_false_path -setup -fall_from $enet_tx_in_clk -rise_to $enet_tx_out_clkset_false_path -hold -rise_from $enet_tx_in_clk -rise_to $enet_tx_out_clkset_false_path -hold -fall_from $enet_tx_in_clk -fall_to $enet_tx_out_clk#**************************************************************# Set Multicycle Path#**************************************************************set_multicycle_path -from $enet_tx_in_clk -to $enet_tx_out_clk -setup -start 2#**************************************************************# Set Maximum Delay#**************************************************************set_max_delay -from $enet_tx_out_clk -to [get_ports {enet_gtx_clk}] 20#**************************************************************# Set Minimum Delay#**************************************************************set_min_delay -from $enet_tx_out_clk -to [get_ports {enet_gtx_clk}] 0