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ABADY1000's avatar
ABADY1000
Icon for New Contributor rankNew Contributor
4 years ago

Setting True LVDS input and output in MAX10

I am creating a new board based on MAX10 FPGA, so I started Pin Planning Project.

As read in MAX10 docs, bank 3 and 4 support True LVDS output, but when I try to set LVDS protocol to the pins in bank 3 or 4 it complains about the absence of "Output Buffer" !

Error (169175): Pin "d337_LVCLK1_P" with LVDS I/O standard needs a differential output buffer which is not available on location T8.
Error (169175): Pin "d337_LV1_P[1]" with LVDS I/O standard needs a differential output buffer which is not available on location U11.
Error (169175): Pin "d337_LV1_P[2]" with LVDS I/O standard needs a differential output buffer which is not available on location V11.
Error (169175): Pin "d337_LV1_P[3]" with LVDS I/O standard needs a differential output buffer which is not available on location V8.
Error (169175): Pin "d337_LV1_P[4]" with LVDS I/O standard needs a differential output buffer which is not available on location V7.
Error (169175): Pin "d337_LVCLK1_P(n)" with LVDS I/O standard needs a differential output buffer which is not available on location T7.
Error (169175): Pin "d337_LV1_P[1](n)" with LVDS I/O standard needs a differential output buffer which is not available on location V12.
Error (169175): Pin "d337_LV1_P[2](n)" with LVDS I/O standard needs a differential output buffer which is not available on location V10.
Error (169175): Pin "d337_LV1_P[3](n)" with LVDS I/O standard needs a differential output buffer which is not available on location U8.
Error (169175): Pin "d337_LV1_P[4](n)" with LVDS I/O standard needs a differential output buffer which is not available on location U7.

Is there something I am missing? because I am sure bank 3 and 4 should support this protocol.

Also when it comes to mini-LVDS and RSDS it shows me this message:

Error (169299): The input pin DIFF0_P[1] has a mini-LVDS I/O standard, but the selected device does not support input pin operation with a mini-LVDS I/O standard.

Isn't mini-LVDS and RSDS supported ?

Emulated protocol works for all banks as expected

8 Replies

  • AndrewG_Intel's avatar
    AndrewG_Intel
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hello @ABADY1000

    Thank you for posting on the Intel® communities.


    We understand that you have some inquiries regarding Intel® Max® 10 FPGA. We have a forum for those specific products and questions so we are moving it to the FPGA, SoC, And CPLD Boards And Kits Forum so it can get answered more quickly.


    Best regards,

    Andrew G.

    Intel Customer Support Technician


  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hello,

    To avoid this error use the Emulated LVDS standard assignment LVDS_E_3R or LVDS_E_1R.

    Thank you.

    • ABADY1000's avatar
      ABADY1000
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hello AminT_Intel,

      I know I can use Emulated protocols, my question is about the true ones, shouldn't MAX10 support them ? Why I can't use them?

      I want to lower the number of resistors on the board and reach faster signals speeds since True protocols capable of handling faster clocks and data rates.

      • AminT_Intel's avatar
        AminT_Intel
        Icon for Regular Contributor rankRegular Contributor
        4 years ago

        Hello,

        There are requirement to do that and you have to follow the right specification (like example the right I/O standard) to be able to do that. Please refer our to our document (Intel® MAX® 10 FPGA Device Datasheet) on your design.

        Thank you