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ABADY1000's avatar
ABADY1000
Icon for New Contributor rankNew Contributor
4 years ago

Setting True LVDS input and output in MAX10

I am creating a new board based on MAX10 FPGA, so I started Pin Planning Project. As read in MAX10 docs, bank 3 and 4 support True LVDS output, but when I try to set LVDS protocol to the pins in b...
AndrewG_Intel's avatar
AndrewG_Intel
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello @ABADY1000

Thank you for posting on the Intel® communities.


We understand that you have some inquiries regarding Intel® Max® 10 FPGA. We have a forum for those specific products and questions so we are moving it to the FPGA, SoC, And CPLD Boards And Kits Forum so it can get answered more quickly.


Best regards,

Andrew G.

Intel Customer Support Technician


  • ABADY1000's avatar
    ABADY1000
    Icon for New Contributor rankNew Contributor
    4 years ago

    Thank you