ABADY1000
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Comparing Cyclone IV power consumption to other FPGAs & SoCs
I have Cyclone IV FPGA and I run a software that reads images from a sensor and apply some image processing algorithm on it, I use Nios II and soft DDR controller . My question is that if I convert my project to other newer chip (Cyclone V, Cyclone 10...etc), would that lower my power consumption? ( running the same project with a newer DDR also - DDR2 or DDR3- ) . And also I face really hard time with soft cores for something like DDR, does having physical DDR controller and CPU would increase power consumption? Because if it doesn't I prefer to use it.843Views0likes3CommentsRe: Setting True LVDS input and output in MAX10
Hello AminT_Intel, Mr. AminT_Intel, the device supports True LVDS as stated in (Intel® MAX® 10 FPGA Device Datasheet), so why I can't use LVDS in these bank3 and 4 pins ?! Please if are willing to help me, give me a good answer, not a general statement.1.7KViews0likes2CommentsRe: Setting True LVDS input and output in MAX10
Hello AminT_Intel, I know I can use Emulated protocols, my question is about the true ones, shouldn't MAX10 support them ? Why I can't use them? I want to lower the number of resistors on the board and reach faster signals speeds since True protocols capable of handling faster clocks and data rates.1.8KViews0likes4CommentsSetting True LVDS input and output in MAX10
I am creating a new board based on MAX10 FPGA, so I started Pin Planning Project. As read in MAX10 docs, bank 3 and 4 support True LVDS output, but when I try to set LVDS protocol to the pins in bank 3 or 4 it complains about the absence of "Output Buffer" ! Error (169175): Pin "d337_LVCLK1_P" with LVDS I/O standard needs a differential output buffer which is not available on location T8. Error (169175): Pin "d337_LV1_P[1]" with LVDS I/O standard needs a differential output buffer which is not available on location U11. Error (169175): Pin "d337_LV1_P[2]" with LVDS I/O standard needs a differential output buffer which is not available on location V11. Error (169175): Pin "d337_LV1_P[3]" with LVDS I/O standard needs a differential output buffer which is not available on location V8. Error (169175): Pin "d337_LV1_P[4]" with LVDS I/O standard needs a differential output buffer which is not available on location V7. Error (169175): Pin "d337_LVCLK1_P(n)" with LVDS I/O standard needs a differential output buffer which is not available on location T7. Error (169175): Pin "d337_LV1_P[1](n)" with LVDS I/O standard needs a differential output buffer which is not available on location V12. Error (169175): Pin "d337_LV1_P[2](n)" with LVDS I/O standard needs a differential output buffer which is not available on location V10. Error (169175): Pin "d337_LV1_P[3](n)" with LVDS I/O standard needs a differential output buffer which is not available on location U8. Error (169175): Pin "d337_LV1_P[4](n)" with LVDS I/O standard needs a differential output buffer which is not available on location U7. Is there something I am missing? because I am sure bank 3 and 4 should support this protocol. Also when it comes to mini-LVDS and RSDS it shows me this message: Error (169299): The input pin DIFF0_P[1] has a mini-LVDS I/O standard, but the selected device does not support input pin operation with a mini-LVDS I/O standard. Isn't mini-LVDS and RSDS supported ? Emulated protocol works for all banks as expected2KViews0likes8Comments