New Contributor
Regular ContributorHello,
To avoid this error use the Emulated LVDS standard assignment LVDS_E_3R or LVDS_E_1R.
Thank you.
New ContributorHello AminT_Intel,
I know I can use Emulated protocols, my question is about the true ones, shouldn't MAX10 support them ? Why I can't use them?
I want to lower the number of resistors on the board and reach faster signals speeds since True protocols capable of handling faster clocks and data rates.
Regular ContributorHello,
There are requirement to do that and you have to follow the right specification (like example the right I/O standard) to be able to do that. Please refer our to our document (Intel® MAX® 10 FPGA Device Datasheet) on your design.
Thank you
New ContributorHello AminT_Intel,
Mr. AminT_Intel, the device supports True LVDS as stated in (Intel® MAX® 10 FPGA Device Datasheet), so why I can't use LVDS in these bank3 and 4 pins ?!
Please if are willing to help me, give me a good answer, not a general statement.
Regular ContributorHello,
True LVDS input buffer is supported in all I/O banks
True LVDS output buffer is only supported on bottom I/O banks.
Please refer to Intel® MAX® 10 High-Speed LVDS I/O User Guide for detailed explanation.
Thank you.
