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ABADY1000's avatar
ABADY1000
Icon for New Contributor rankNew Contributor
3 years ago

Setting True LVDS input and output in MAX10

I am creating a new board based on MAX10 FPGA, so I started Pin Planning Project. As read in MAX10 docs, bank 3 and 4 support True LVDS output, but when I try to set LVDS protocol to the pins in b...
AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,

To avoid this error use the Emulated LVDS standard assignment LVDS_E_3R or LVDS_E_1R.

Thank you.

  • ABADY1000's avatar
    ABADY1000
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello AminT_Intel,

    I know I can use Emulated protocols, my question is about the true ones, shouldn't MAX10 support them ? Why I can't use them?

    I want to lower the number of resistors on the board and reach faster signals speeds since True protocols capable of handling faster clocks and data rates.

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hello,

      There are requirement to do that and you have to follow the right specification (like example the right I/O standard) to be able to do that. Please refer our to our document (Intel® MAX® 10 FPGA Device Datasheet) on your design.

      Thank you

      • ABADY1000's avatar
        ABADY1000
        Icon for New Contributor rankNew Contributor
        3 years ago

        Hello AminT_Intel,

        Mr. AminT_Intel, the device supports True LVDS as stated in (Intel® MAX® 10 FPGA Device Datasheet), so why I can't use LVDS in these bank3 and 4 pins ?!

        Please if are willing to help me, give me a good answer, not a general statement.