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Hello AminT_Intel,
I know I can use Emulated protocols, my question is about the true ones, shouldn't MAX10 support them ? Why I can't use them?
I want to lower the number of resistors on the board and reach faster signals speeds since True protocols capable of handling faster clocks and data rates.
Hello,
There are requirement to do that and you have to follow the right specification (like example the right I/O standard) to be able to do that. Please refer our to our document (Intel® MAX® 10 FPGA Device Datasheet) on your design.
Thank you
- ABADY10004 years ago
New Contributor
Hello AminT_Intel,
Mr. AminT_Intel, the device supports True LVDS as stated in (Intel® MAX® 10 FPGA Device Datasheet), so why I can't use LVDS in these bank3 and 4 pins ?!
Please if are willing to help me, give me a good answer, not a general statement.
- AminT_Intel4 years ago
Regular Contributor
Hello,
True LVDS input buffer is supported in all I/O banks
True LVDS output buffer is only supported on bottom I/O banks.
Please refer to Intel® MAX® 10 High-Speed LVDS I/O User Guide for detailed explanation.
Thank you.
- AminT_Intel4 years ago
Regular Contributor
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.