srinivasan
Occasional Contributor
3 years agoPcie loopback in the end point
Hello sir,
I am using Arria 10 Pcie Hard IP in Arria 10 SOC development kit , Here I am configuring IP as Pcie root complex (Master FPGA) and need to acheive the loop back mode at the end point(other device). For that I need to configure the TS1 Loopback bit set in the root complex to enable loop back mode at the end point.
Here My query is how/where I need to set the TS1 loopback bit in the Pcie root complex design to enable loop back at the end point.So Please share me the Corresponding Registers and steps need to be followed in the Design. If possible please share the End point loop back and root complex reference design.
Regards,
Srinivasan.