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srinivasan's avatar
srinivasan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Pcie loopback in the end point

Hello sir, I am using Arria 10 Pcie Hard IP in Arria 10 SOC development kit , Here I am configuring IP as Pcie root complex (Master FPGA) and need to acheive the loop back mode at the end ...
srinivasan's avatar
srinivasan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Thanks for the reply,

Hello chuan,

What you shared is correct, but I want to send the loopback configuration packet from the root complex design to end point.

Please send the screenshot of the loopback register used in the implemented root complex design.

Note: End point should be in loopback mode

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


I dont really get your question , Can you describe more detail ?
Do you means that the document does not address what you want or other

Regards,

Wei Chuan