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srinivasan's avatar
srinivasan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Pcie loopback in the end point

Hello sir, I am using Arria 10 Pcie Hard IP in Arria 10 SOC development kit , Here I am configuring IP as Pcie root complex (Master FPGA) and need to acheive the loop back mode at the end ...
srinivasan's avatar
srinivasan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi,

Finally, Please send the Configuration loopback register access RTL code for root complex design.

Note: Not whole design, only configuration RTL code(Verilog/VHDL file).