Forum Discussion
srinivasan
Occasional Contributor
Occasional ContributorPcie loopback in the end point
Hello sir,
I am using Arria 10 Pcie Hard IP in Arria 10 SOC development kit , Here I am configuring IP as Pcie root complex (Master FPGA) and need to acheive the loop back mode at the end ...
srinivasanOccasional Contributor
Occasional ContributorThanks for the reply,
Hello chuan,
What you shared is correct, but I want to send the loopback configuration packet from the root complex design to end point.
Please send the screenshot of the loopback register used in the implemented root complex design.
Note: End point should be in loopback mode
Wincent_Altera
Regular Contributor
Regular ContributorHi,
If you want to know how to set the loopback mode, Please refer to Arria 10 Soc User guide under Section 4.13
https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/arria10/soc/es2_files/A10-SoC-DK-UG_2.pdf
Let me know if this answered your question.
Regards,
Wincent_Intel
