Forum Discussion
srinivasan
Occasional Contributor
Occasional ContributorPcie loopback in the end point
Hello sir,
I am using Arria 10 Pcie Hard IP in Arria 10 SOC development kit , Here I am configuring IP as Pcie root complex (Master FPGA) and need to acheive the loop back mode at the end ...
Wincent_Altera
Regular Contributor
Regular ContributorHi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
